MPU-6050 6-axis accelerometer/gyroscope | I2C Device Library (2023)

Auxiliary I2C Supply Selection (AUX_VDDIO @ 0x00)

Register Bitfields

• [7] AUX_VDDIO
• [6:1] XG_OFFS_TC
• [0] OTP_BNK_VLD

This register specifies the auxiliary I2C supply voltage level. Bits 6 through 0 are reserved.

AUX_VDDIO @ 0x00

AUX_VDDIO [7]

Options

• 0 = VLOGIC
• 1 = VDD

AUX_VDDIO configures the high logic level of the auxiliary I2C bus to be either VLOGIC or VDD. When set to 1, the auxiliary I2C bus high logic level is VDD. When cleared to 0, the auxiliary I2C bus high logic level is VLOGIC.

Sample Rate Divider (SMPLRT_DIV @ 0x19)

Register Bitfields

• [7:0] SMPLRT_DIV

This register specifies the divider from the gyroscope output rate used to generate the Sample Rate for the MPU-60X0.The sensor register output, FIFO output, DMP sampling, Motion detection, Zero Motion detection, and Free Fall detection are all based on the Sample Rate.The Sample Rate is generated by dividing the gyroscope output rate by SMPLRT_DIV:Sample Rate = Gyroscope Output Rate / (1 + SMPLRT_DIV)where Gyroscope Output Rate = 8kHz when the DLPF is disabled (DLPF_CFG = 0 or 7), and 1kHz when the DLPF is enabled (see Register 26).Note: The accelerometer output rate is 1kHz. This means that for a Sample Rate greater than 1kHz, the same accelerometer sample may be output to the FIFO, DMP, and sensor registers more than once.For a diagram of the gyroscope and accelerometer signal paths, see Section 8 of the MPU-6000/MPU-6050 Product Specification document.

SMPLRT_DIV @ 0x19

SMPLRT_DIV [7:0]

8-bit unsigned value. The Sample Rate is determined by dividing the gyroscope output rate by this value.

Configuration (CONFIG @ 0x1A)

Register Bitfields

• [5:3] EXT_SYNC_SET
• [2:0] DLPF_CFG

This register configures the external Frame Synchronization (FSYNC) pin sampling and the Digital Low Pass Filter (DLPF) setting for both the gyroscopes and accelerometers.An external signal connected to the FSYNC pin can be sampled by configuring EXT_SYNC_SET.Signal changes to the FSYNC pin are latched so that short strobes may be captured. The latched FSYNC signal will be sampled at the Sampling Rate, as defined in register 25. After sampling, the latch will reset to the current FSYNC signal state.The sampled value will be reported in place of the least significant bit in a sensor data register determined by the value of EXT_SYNC_SET according to the following table.EXT_SYNC_SET FSYNC Bit Location0 Input disabled1 TEMP_OUT_L[0]2 GYRO_XOUT_L[0]3 GYRO_YOUT_L[0]4 GYRO_ZOUT_L[0]5 ACCEL_XOUT_L[0]6 ACCEL_YOUT_L[0]7 ACCEL_ZOUT_L[0]The DLPF is configured by DLPF_CFG. The accelerometer and gyroscope are filtered according to the value of DLPF_CFG as shown in the table below.DLPF_CFG Accelerometer (Fs = 1kHz) GyroscopeBandwidth (Hz) Delay (ms) Bandwidth (Hz) Delay (ms) Fs (kHz)0 260 0 256 0.98 81 184 2.0 188 1.9 12 94 3.0 98 2.8 13 44 4.9 42 4.8 14 21 8.5 20 8.3 15 10 13.8 10 13.4 16 5 19.0 5 18.6 17 RESERVED RESERVED 8Bit 7 and bit 6 are reserved.

CONFIG @ 0x1A

EXT_SYNC_SET [5:3]

Options

• 0 = Input disabled
• 1 = TEMP_OUT_L[0]
• 2 = GYRO_XOUT_L[0]
• 3 = GYRO_YOUT_L[0]
• 4 = GYRO_ZOUT_L[0]
• 5 = ACCEL_XOUT_L[0]
• 6 = ACCEL_YOUT_L[0]
• 7 = ACCEL_ZOUT_L[0]

3-bit unsigned value. Configures the FSYNC pin sampling.

CONFIG @ 0x1A

DLPF_CFG [2:0]

Options

• 0 = 260 Hz, 0 ms / 256 Hz, 0.98 ms, 8 kHz
• 1 = 184 Hz, 2.0 ms / 188 Hz, 1.9 ms, 1 kHz
• 2 = 94 Hz, 3.0 ms / 98 Hz, 2.8 1 ms, kHz
• 3 = 44 Hz, 4.9 ms / 42 Hz, 4.8 1 ms, kHz
• 4 = 21 Hz, 8.5 ms / 20 Hz, 8.3 1 ms, kHz
• 5 = 10 Hz, 13.8 ms / 10 Hz, 13.4 ms, 1 kHz
• 6 = 5 Hz, 19.0 ms / 5 Hz, 18.6 1 ms, kHz
• 7 = RESERVED / RESERVED, 8 kHz

3-bit unsigned value. Configures the DLPF setting

Gyroscope Configuration (GYRO_CONFIG @ 0x1B)

Register Bitfields

• [7] XG_ST
• [6] YG_ST
• [5] ZG_ST
• [4:3] FS_SEL

This register is used to trigger gyroscope self-test and configure the gyroscopes’ full scale range.Gyroscope self-test permits users to test the mechanical and electrical portions of the gyroscope. The self-test for each gyroscope axis can be activated by controlling the XG_ST, YG_ST, and ZG_ST bits of this register. Self-test for each axis may be performed independently or all at the same time.When self-test is activated, the on-board electronics will actuate the appropriate sensor. This actuation will move the sensor’s proof masses over a distance equivalent to a pre-defined Coriolis force. This proof mass displacement results in a change in the sensor output, which is reflected in the output signal. The output signal is used to observe the self-test response.The self-test response is defined as follows:Self-test response = Sensor output with self-test enabled – Sensor output without selftest enabledThe self-test limits for each gyroscope axis is provided in the electrical characteristics tables of the MPU-6000/MPU-6050 Product Specification document. When the value of the self-test response is within the min/max limits of the product specification, the part has passed self test. When the self-test response exceeds the min/max values specified in the document, the part is deemed to have failed self-test. FS_SEL selects the full scale range of the gyroscope outputs according to the following table.FS_SEL Full Scale Range0 ± 250 °/s1 ± 500 °/s2 ± 1000 °/s3 ± 2000 °/sBits 2 through 0 are reserved.

GYRO_CONFIG @ 0x1B

XG_ST [7]

Setting this bit causes the X axis gyroscope to perform self test.

GYRO_CONFIG @ 0x1B

YG_ST [6]

Setting this bit causes the Y axis gyroscope to perform self test.

GYRO_CONFIG @ 0x1B

ZG_ST [5]

Setting this bit causes the Z axis gyroscope to perform self test.

GYRO_CONFIG @ 0x1B

FS_SEL [4:3]

Options

• 0 = ± 250 °/s, 131 LSB/°/s
• 1 = ± 500 °/s, 65.5 LSB/°/s
• 2 = ± 1000 °/s, 32.8 LSB/°/s
• 3 = ± 2000 °/s, 16.4 LSB/°/s

2-bit unsigned value. Selects the full scale range of gyroscopes.

Accelerometer Configuration (ACCEL_CONFIG @ 0x1C)

Register Bitfields

• [7] XA_ST
• [6] YA_ST
• [5] ZA_ST
• [4:3] AFS_SEL
• [2:0] ACCEL_HPF

This register is used to trigger accelerometer self test and configure the accelerometer full scale range. This register also configures the Digital High Pass Filter (DHPF).Accelerometer self-test permits users to test the mechanical and electrical portions of the accelerometer. The self-test for each accelerometer axis can be activated by controlling the XA_ST, YA_ST, and ZA_ST bits of this register. Self-test for each axis may be performed independently or all at the same time.When self-test is activated, the on-board electronics will actuate the appropriate sensor. This actuation simulates an external force. The actuated sensor, in turn, will produce a corresponding output signal. The output signal is used to observe the self-test response. The self-test response is defined as follows:Self-test response = Sensor output with self-test enabled – Sensor output without self-test enabledThe self-test limits for each accelerometer axis is provided in the electrical characteristics tables of the MPU-6000/MPU-6050 Product Specification document. When the value of the self-test response is within the min/max limits of the product specification, the part has passed self test. When the selftest response exceeds the min/max values specified in the document, the part is deemed to have failed self-test.AFS_SEL selects the full scale range of the accelerometer outputs according to the following table.AFS_SEL Full Scale Range0 ± 2g1 ± 4g2 ± 8g3 ± 16g

ACCEL_CONFIG @ 0x1C

XA_ST [7]

When set to 1, the X-Axis accelerometer performs self test.

ACCEL_CONFIG @ 0x1C

YA_ST [6]

When set to 1, the Y-Axis accelerometer performs self test.

ACCEL_CONFIG @ 0x1C

ZA_ST [5]

When set to 1, the Z-Axis accelerometer performs self test.

ACCEL_CONFIG @ 0x1C

AFS_SEL [4:3]

Options

• 0 = ± 2g, 16384 LSB/mg
• 1 = ± 4g, 8192 LSB/mg
• 2 = ± 8g, 4096 LSB/mg
• 3 = ± 16g, 2048 LSB/mg

2-bit unsigned value. Selects the full scale range of accelerometers.

ACCEL_CONFIG @ 0x1C

ACCEL_HPF [2:0]

Options

• 0 = Reset
• 1 = On @ 5 Hz
• 2 = On @ 2.5 Hz
• 3 = On @ 1.25 Hz
• 4 = On @ 0.63 Hz
• 7 = Hold

3-bit unsigned value. Selects the Digital High Pass Filter configuration.ACCEL_HPF configures the DHPF available in the path leading to motion detectors (Free Fall, Motion threshold, and Zero Motion). The high pass filter output is not available to the data registers (see Figure in Section 8 of the MPU-6000/MPU-6050 Product Specification document).The high pass filter has three modes: - Reset: The filter output settles to zero within one sample. This effectively disables the high pass filter. This mode may be toggled to quickly settle the filter.- On: The high pass filter will pass signals above the cut off frequency.- Hold: When triggered, the filter holds the present sample. The filter output will be the difference between the input sample and the held sample.ACCEL_HPF Filter Mode Cut-off Frequency0 Reset None1 On 5Hz2 On 2.5Hz3 On 1.25Hz4 On 0.63Hz7 Hold None

Free Fall Acceleration Threshold (FF_THR @ 0x1D)

Register Bitfields

• [7:0] FF_THR

This register configures the detection threshold for Free Fall event detection. The mg per LSB increment for FF_THR can be found in the Electrical Specifications table of the MPU-6000/MPU-6050 Product Specification document.Free Fall is detected when the absolute value of the accelerometer measurements for the three axes are each less than the detection threshold. This condition increments the Free Fall duration counter (Register 30). The Free Fall interrupt is triggered when the Free Fall duration counter reaches the time specified in FF_DUR (Register 30).For more details on the Free Fall detection interrupt, see Section 8.2 of the MPU-6000/MPU-6050 Product Specification document as well as Registers 56 and 58 of this document.

FF_THR @ 0x1D

FF_THR [7:0]

8-bit unsigned value specifying the Free Fall detection threshold.

Free Fall Duration (FF_DUR @ 0x1E)

Register Bitfields

• [7:0] FF_DUR

This register configures the duration counter threshold for Free Fall event detection. The duration counter ticks at 1kHz, therefore FF_DUR has a unit of 1 LSB = 1 ms.The Free Fall duration counter increments while the absolute value of the accelerometer measurements are each less than the detection threshold (Register 29). The Free Fall interrupt is triggered when the Free Fall duration counter reaches the time specified in this register. For more details on the Free Fall detection interrupt, see Section 8.2 of the MPU-6000/MPU-6050 Product Specification document as well as Registers 56 and 58 of this document.

FF_DUR @ 0x1E

FF_DUR [7:0]

8-bit unsigned value. Specifies the duration counter threshold. Unit of LSB = 1ms.

Motion Detection Threshold (MOT_THR @ 0x1F)

Register Bitfields

• [7:0] MOT_THR

This register configures the detection threshold for Motion interrupt generation. The mg per LSB increment for MOT_THR can be found in the Electrical Specifications table of the MPU-6000/MPU-6050 Product Specification document.Motion is detected when the absolute value of any of the accelerometer measurements exceeds this Motion detection threshold. This condition increments the Motion detection duration counter (Register 32). The Motion detection interrupt is triggered when the Motion Detection counter reaches the time count specified in MOT_DUR (Register 32).The Motion interrupt will indicate the axis and polarity of detected motion in MOT_DETECT_STATUS (Register 97).For more details on the Motion detection interrupt, see Section 8.3 of the MPU-6000/MPU-6050 Product Specification document as well as Registers 56 and 58 of this document.

MOT_THR @ 0x1F

MOT_THR [7:0]

8-bit unsigned value. Specifies the Motion detection threshold.

Motion Detection Duration (MOT_DUR @ 0x20)

Register Bitfields

• [7:0] MOT_DUR

This register configures the duration counter threshold for Motion interrupt generation. The duration counter ticks at 1 kHz, therefore MOT_DUR has a unit of 1 LSB = 1 ms.The Motion detection duration counter increments when the absolute value of any of the accelerometer measurements exceeds the Motion detection threshold (Register 31). The Motion detection interrupt is triggered when the Motion detection counter reaches the time count specified in this register. For more details on the Motion detection interrupt, see Section 8.3 of the MPU-6000/MPU-6050 Product Specification document

MOT_DUR @ 0x20

MOT_DUR [7:0]

8-bit unsigned value. Specifies the duration counter threshold. Unit of 1 LSB = 1ms.

Zero Motion Detection Threshold (ZRMOT_THR @ 0x21)

Register Bitfields

• [7:0] ZRMOT_THR

This register configures the detection threshold for Zero Motion interrupt generation. The mg per LSB increment for ZRMOT_THR can be found in the Electrical Specifications table of the MPU-6000/MPU-6050 Product Specification document.Zero Motion is detected when the absolute value of the accelerometer measurements for the 3 axes are each less than the detection threshold. This condition increments the Zero Motion duration counter (Register 34). The Zero Motion interrupt is triggered when the Zero Motion duration counter reaches the time count specified in ZRMOT_DUR (Register 34).Unlike Free Fall or Motion detection, Zero Motion detection triggers an interrupt both when Zero Motion is first detected and when Zero Motion is no longer detected.When a zero motion event is detected, a Zero Motion Status will be indicated in the MOT_DETECT_STATUS register (Register 97). When a motion-to-zero-motion condition is detected, the status bit is set to 1. When a zero-motion-to-motion condition is detected, the status bit is set to 0.For more details on the Zero Motion detection interrupt, see Section 8.4 of the MPU-6000/MPU-6050 Product Specification document as well as Registers 56 and 58 of this document.

ZRMOT_THR @ 0x21

ZRMOT_THR [7:0]

8-bit unsigned value. Specifies the Zero Motion detection threshold.

Zero Motion Detection Duration (ZRMOT_DUR @ 0x22)

Register Bitfields

• [7:0] ZRMOT_DUR

This register configures the duration counter threshold for Zero Motion interrupt generation. The duration counter ticks at 16 Hz, therefore ZRMOT_DUR has a unit of 1 LSB = 64 ms.The Zero Motion duration counter increments while the absolute value of the accelerometer measurements are each less than the detection threshold (Register 33). The Zero Motion interrupt is triggered when the Zero Motion duration counter reaches the time count specified in this register.For more details on the Zero Motion detection interrupt, see Section 8.4 of the MPU-6000/MPU-6050 Product Specification document, as well as Registers 56 and 58 of this document.

ZRMOT_DUR @ 0x22

ZRMOT_DUR [7:0]

8-bit unsigned value. Specifies the duration counter threshold. Unit of 1 LSB = 64ms.

FIFO Enable (FIFO_EN @ 0x23)

Register Bitfields

• [7] TEMP_FIFO_EN
• [6] XG_FIFO_EN
• [5] YG_FIFO_EN
• [4] ZG_FIFO_EN
• [3] ACCEL_FIFO_EN
• [2] SLV2_FIFO_EN
• [1] SLV1_FIFO_EN
• [0] SLV0_FIFO_EN

This register determines which sensor measurements are loaded into the FIFO buffer.Data stored inside the sensor data registers (Registers 59 to 96) will be loaded into the FIFO buffer if a sensor’s respective FIFO_EN bit is set to 1 in this register.When a sensor’s FIFO_EN bit is enabled in this register, data from the sensor data registers will be loaded into the FIFO buffer. The sensors are sampled at the Sample Rate as defined in Register 25. For further information regarding sensor data registers, please refer to Registers 59 to 96.When an external Slave’s corresponding FIFO_EN bit (SLVx_FIFO_EN, where x=0, 1, or 2) is set to 1, the data stored in its corresponding data registers (EXT_SENS_DATA registers, Registers 73 to 96) will be written into the FIFO buffer at the Sample Rate. EXT_SENS_DATA register association with I2C Slaves is determined by the I2C_SLVx_CTRL registers (where x=0, 1, or 2; Registers 39, 42, and 45). For information regarding EXT_SENS_DATA registers, please refer to Registers 73 to 96.Note that the corresponding FIFO_EN bit (SLV3_FIFO_EN) is found in I2C_MST_CTRL (Register 36). Also note that Slave 4 behaves in a different manner compared to Slaves 0-3. Please refer to Registers 49 to 53 for further information regarding Slave 4 usage.

FIFO_EN @ 0x23

TEMP_FIFO_EN [7]

When set to 1, this bit enables TEMP_OUT_H and TEMP_OUT_L (Registers 65 and 66) to be written into the FIFO buffer.

FIFO_EN @ 0x23

XG_FIFO_EN [6]

When set to 1, this bit enables GYRO_XOUT_H and GYRO_XOUT_L (Registers 67 and 68) to be written into the FIFO buffer.

FIFO_EN @ 0x23

YG_FIFO_EN [5]

When set to 1, this bit enables GYRO_YOUT_H and GYRO_YOUT_L (Registers 69 and 70) to be written into the FIFO buffer.

FIFO_EN @ 0x23

ZG_FIFO_EN [4]

When set to 1, this bit enables GYRO_ZOUT_H and GYRO_ZOUT_L (Registers 71 and 72) to be written into the FIFO buffer.

FIFO_EN @ 0x23

ACCEL_FIFO_EN [3]

When set to 1, this bit enables ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H, and ACCEL_ZOUT_L (Registers 59 to 64) to be written into the FIFO buffer.

FIFO_EN @ 0x23

SLV2_FIFO_EN [2]

When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96) associated with Slave 2 to be written into the FIFO buffer.

FIFO_EN @ 0x23

SLV1_FIFO_EN [1]

When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96) associated with Slave 1 to be written into the FIFO buffer.

FIFO_EN @ 0x23

SLV0_FIFO_EN [0]

When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96) associated with Slave 0 to be written into the FIFO buffer.

I2C Master Control (I2C_MST_CTRL @ 0x24)

Register Bitfields

• [7] MULT_MST_EN
• [6] WAIT_FOR_ES
• [5] SLV_3_FIFO_EN
• [4] I2C_MST_P_NSR
• [3:0] I2C_MST_CLK

This register configures the auxiliary I2C bus for single-master or multi-master control. In addition, the register is used to delay the Data Ready interrupt, and also enables the writing of Slave 3 data into the FIFO buffer. The register also configures the auxiliary I2C Master’s transition from one slave read to the next, as well as the MPU-60X0’s 8MHz internal clock.Multi-master capability allows multiple I2C masters to operate on the same bus. In circuits where multi-master capability is required, set MULT_MST_EN to 1. This will increase current drawn by approximately 30μA.In circuits where multi-master capability is required, the state of the I2C bus must always be monitored by each separate I2C Master. Before an I2C Master can assume arbitration of the bus, it must first confirm that no other I2C Master has arbitration of the bus. When MULT_MST_EN is set to 1, the MPU-60X0’s bus arbitration detection logic is turned on, enabling it to detect when the bus is available.When the WAIT_FOR_ES bit is set to 1, the Data Ready interrupt will be delayed until External Sensor data from the Slave Devices are loaded into the EXT_SENS_DATA registers. This is used to ensure that both the internal sensor data (i.e. from gyro and accel) and external sensor data have been loaded to their respective data registers (i.e. the data is synced) when the Data Ready interrupt is triggered.When the Slave 3 FIFO enable bit (SLV_3_FIFO_EN) is set to 1, Slave 3 sensor measurement data will be loaded into the FIFO buffer each time. EXT_SENS_DATA register association with I2C Slaves is determined by I2C_SLV3_CTRL (Register 48).For further information regarding EXT_SENS_DATA registers, please refer to Registers 73 to 96.The corresponding FIFO_EN bits for Slave 0, Slave 1, and Slave 2 can be found in Register 35.The I2C_MST_P_NSR bit configures the I2C Master’s transition from one slave read to the next slave read. If the bit equals 0, there will be a restart between reads. If the bit equals 1, there will be a stop followed by a start of the following read. When a write transaction follows a read transaction, the stop followed by a start of the successive write will be always used.

I2C_MST_CTRL @ 0x24

MULT_MST_EN [7]

When set to 1, this bit enables multi-master capability.

I2C_MST_CTRL @ 0x24

WAIT_FOR_ES [6]

When set to 1, this bit delays the Data Ready interrupt until External Sensor data from the Slave devices have been loaded into the EXT_SENS_DATA registers.

I2C_MST_CTRL @ 0x24

SLV_3_FIFO_EN [5]

When set to 1, this bit enables EXT_SENS_DATA registers associated with Slave 3 to be written into the FIFO. The corresponding bits for Slaves 0-2 can be found in Register 35.

I2C_MST_CTRL @ 0x24

I2C_MST_P_NSR [4]

Controls the I2C Master’s transition from one slave read to the next slave read.When this bit equals 0, there is a restart between reads.When this bit equals 1, there is a stop and start marking the beginning of the next read.When a write follows a read, a stop and start is always enforced.

I2C_MST_CTRL @ 0x24

I2C_MST_CLK [3:0]

Options

• 0 = 348 kHz / 23
• 1 = 333 kHz / 24
• 2 = 320 kHz / 25
• 3 = 308 kHz / 26
• 4 = 296 kHz / 27
• 5 = 286 kHz / 28
• 6 = 276 kHz / 29
• 7 = 267 kHz / 30
• 8 = 258 kHz / 31
• 9 = 500 kHz / 16
• 10 = 471 kHz / 17
• 11 = 444 kHz / 18
• 12 = 421 kHz / 19
• 13 = 400 kHz / 20
• 14 = 381 kHz / 21
• 15 = 364 kHz / 22

I2C_MST_CLK is a 4 bit unsigned value which configures a divider on the MPU-60X0 internal 8MHz clock. It sets the I2C master clock speed according to the following table:I2C_MST_CLK I2C Master Clock Speed 8MHz Clock Divider0 348 kHz 231 333 kHz 242 320 kHz 253 308 kHz 264 296 kHz 275 286 kHz 286 276 kHz 297 267 kHz 308 258 kHz 319 500 kHz 1610 471 kHz 1711 444 kHz 1812 421 kHz 1913 400 kHz 2014 381 kHz 2115 364 kHz 22

I2C Slave 0 Address (I2C_SLV0_ADDR @ 0x25)

Register Bitfields

• [7] I2C_SLV0_RW
• [6:0] I2C_SLV0_ADDR

Configures the device address and data transfer mode for Slave 0. I2C data transactions are performed at the Sample Rate, as defined in Register 25. The user is responsible for ensuring that I2C data transactions to and from each enabled Slave can be completed within a single period of the Sample Rate.The I2C slave access rate can be reduced relative to the Sample Rate. This reduced access rate is determined by I2C_MST_DLY (Register 52). Whether a slave’s access rate is reduced relative to the Sample Rate is determined by I2C_MST_DELAY_CTRL (Register 103).The processing order for the slaves is fixed. The sequence followed for processing the slaves is Slave 0, Slave 1, Slave 2, Slave 3 and Slave 4. If a particular Slave is disabled it will be skipped.Each slave can either be accessed at the sample rate or at a reduced sample rate. In a case where some slaves are accessed at the Sample Rate and some slaves are accessed at the reduced rate, the sequence of accessing the slaves (Slave 0 to Slave 4) is still followed. However, the reduced rate slaves will be skipped if their access rate dictates that they should not be accessed during that particular cycle. For further information regarding the reduced access rate, please refer to Register 52. Whether a slave is accessed at the Sample Rate or at the reduced rate is determined by the Delay Enable bits in Register 103.Byte Swapping ExampleThe following example demonstrates byte swapping for I2C_SLV0_BYTE_SW = 1, I2C_SLV0_GRP = 0, I2C_SLV0_REG = 0x01, and I2C_SLV0_LEN = 0x4:1. The first byte, read from Slave 0 register 0x01, will be stored at EXT_SENS_DATA_00. Because I2C_SLV0_GRP = 0, bytes from even, then odd register addresses will be paired together as word pairs. Since the read operation started from an odd register address instead of an even address, only one byte is read.2. The second and third bytes will be swapped, since I2C_SLV0_BYTE_SW = 1 and I2C_SLV0_REG[0] = 1. The data read from 0x02 will be stored at EXT_SENS_DATA_02, and the data read from 0x03 will be stored at EXT_SENS_DATA_01.3. The last byte, read from address 0x04, will be stored at EXT_SENS_DATA_03. Because there is only one byte remaining in the read operation, byte swapping will not occur.Slave Access ExampleSlave 0 is accessed at the Sample Rate, while Slave 1 is accessed at half the Sample Rate. The other slaves are disabled. In the first cycle, both Slave 0 and Slave 1 will be accessed. However, in the second cycle, only Slave 0 will be accessed. In the third cycle, both Slave 0 and Slave 1 will be accessed. In the fourth cycle, only Slave 0 will be accessed. This pattern continues.

I2C_SLV0_ADDR @ 0x25

I2C_SLV0_RW [7]

I2C slave data transactions between the MPU-60X0 and Slave 0 are set as either read or write operations by the I2C_SLV0_RW bit. When this bit is 1, the transfer is a read operation. When the bit is 0, the transfer is a write operation.In read mode, the result of the read is placed in the lowest available EXT_SENS_DATA register. For further information regarding the allocation of read results, please refer to the EXT_SENS_DATA register description (Registers 73 – 96). In write mode, the contents of I2C_SLV0_DO (Register 99) will be written to the slave device.

I2C_SLV0_ADDR @ 0x25

I2C_SLV0_ADDR [6:0]

Specifies the 7-bit I2C slave address of Slave 0.

I2C Slave 0 Register (I2C_SLV0_REG @ 0x26)

Register Bitfields

• [7:0] I2C_SLV0_REG

I2C_SLV0_REG @ 0x26

I2C_SLV0_REG [7:0]

Specifies the internal register at which to begin data transfer within Slave 0.

I2C Slave 0 Control (I2C_SLV0_CTRL @ 0x27)

Register Bitfields

• [7] I2C_SLV0_EN
• [6] I2C_SLV0_BYTE_SW
• [5] I2C_SLV0_REG_DIS
• [4] I2C_SLV0_GRP
• [3:0] I2C_SLV0_LEN

I2C_SLV0_CTRL @ 0x27

I2C_SLV0_EN [7]

Enables Slave 0 for I2C data transaction. A data transaction is performed only if more than zero bytes are to be transferred (I2C_SLV0_LEN > 0) between an enabled slave device (I2C_SLV0_EN = 1).

I2C_SLV0_CTRL @ 0x27

I2C_SLV0_BYTE_SW [6]

Configures byte swapping of word pairs. When byte swapping is enabled, the high and low bytes of a word pair are swapped. Please refer to I2C_SLV0_GRP for the pairing convention of the word pairs. When this bit is cleared to 0, bytes transferred to and from Slave 0 will be written to EXT_SENS_DATA registers in the order they were transferred.

I2C_SLV0_CTRL @ 0x27

I2C_SLV0_REG_DIS [5]

Disable slave register address sending. When set to 1, the transaction will read or write data only. When cleared to 0, the transaction will write a register address prior to reading or writing data. This bit should equal 0 when specifying the register address within the Slave device to/from which the ensuing data transaction will take place.

I2C_SLV0_CTRL @ 0x27

I2C_SLV0_GRP [4]

Specifies the grouping order of word pairs received from registers. When cleared to 0, bytes from register addresses 0 and 1, 2 and 3, etc (even, then odd register addresses) are paired to form a word. When set to 1, bytes from register addresses are paired 1 and 2, 3 and 4, etc. (odd, then even register addresses) are paired to form a word.

I2C_SLV0_CTRL @ 0x27

I2C_SLV0_LEN [3:0]

The number of bytes transferred is specified by I2C_SLV0_LEN. When more than 1 byte is transferred (I2C_SLV0_LEN > 1), data is read from (written to) sequential addresses starting from I2C_SLV0_REG.

I2C Slave 1 Address (I2C_SLV1_ADDR @ 0x28)

Register Bitfields

• [7] I2C_SLV1_RW
• [6:0] I2C_SLV1_ADDR

Configures the device address and data transfer mode for Slave 1. I2C data transactions are performed at the Sample Rate, as defined in Register 25. The user is responsible for ensuring that I2C data transactions to and from each enabled Slave can be completed within a single period of the Sample Rate.The I2C slave access rate can be reduced relative to the Sample Rate. This reduced access rate is determined by I2C_MST_DLY (Register 52). Whether a slave’s access rate is reduced relative to the Sample Rate is determined by I2C_MST_DELAY_CTRL (Register 103).The processing order for the slaves is fixed. The sequence followed for processing the slaves is Slave 0, Slave 1, Slave 2, Slave 3 and Slave 4. If a particular Slave is disabled it will be skipped.Each slave can either be accessed at the sample rate or at a reduced sample rate. In a case where some slaves are accessed at the Sample Rate and some slaves are accessed at the reduced rate, the sequence of accessing the slaves (Slave 0 to Slave 4) is still followed. However, the reduced rate slaves will be skipped if their access rate dictates that they should not be accessed during that particular cycle. For further information regarding the reduced access rate, please refer to Register 52. Whether a slave is accessed at the Sample Rate or at the reduced rate is determined by the Delay Enable bits in Register 103.

I2C_SLV1_ADDR @ 0x28

I2C_SLV1_RW [7]

I2C slave data transactions between the MPU-60X0 and Slave 1 are set as either read or write operations by the I2C_SLV1_RW bit. When this bit is 1, the transfer is a read operation. When the bit is 0, the transfer is a write operation.In read mode, the result of the read is placed in the lowest available EXT_SENS_DATA register. For further information regarding the allocation of read results, please refer to the EXT_SENS_DATA register description (Registers 73 – 96). In write mode, the contents of I2C_SLV1_DO (Register 99) will be written to the slave device.

I2C_SLV1_ADDR @ 0x28

I2C_SLV1_ADDR [6:0]

Specifies the 7-bit I2C slave address of Slave 1.

I2C Slave 1 Register (I2C_SLV1_REG @ 0x29)

Register Bitfields

• [7:0] I2C_SLV1_REG

I2C_SLV1_REG @ 0x29

I2C_SLV1_REG [7:0]

Specifies the internal register at which to begin data transfer within Slave 1.

I2C Slave 1 Control (I2C_SLV1_CTRL @ 0x2A)

Register Bitfields

• [7] I2C_SLV1_EN
• [6] I2C_SLV1_BYTE_SW
• [5] I2C_SLV1_REG_DIS
• [4] I2C_SLV1_GRP
• [3:0] I2C_SLV1_LEN

I2C_SLV1_CTRL @ 0x2A

I2C_SLV1_EN [7]

Enables Slave 1 for I2C data transaction. A data transaction is performed only if more than zero bytes are to be transferred (I2C_SLV1_LEN > 0) between an enabled slave device (I2C_SLV1_EN = 1).

I2C_SLV1_CTRL @ 0x2A

I2C_SLV1_BYTE_SW [6]

Configures byte swapping of word pairs. When byte swapping is enabled, the high and low bytes of a word pair are swapped. Please refer to I2C_SLV1_GRP for the pairing convention of the word pairs. When this bit is cleared to 0, bytes transferred to and from Slave 1 will be written to EXT_SENS_DATA registers in the order they were transferred.

I2C_SLV1_CTRL @ 0x2A

I2C_SLV1_REG_DIS [5]

Disable slave register address sending. When set to 1, the transaction will read or write data only. When cleared to 0, the transaction will write a register address prior to reading or writing data. This bit should equal 0 when specifying the register address within the Slave device to/from which the ensuing data transaction will take place.

I2C_SLV1_CTRL @ 0x2A

I2C_SLV1_GRP [4]

Specifies the grouping order of word pairs received from registers. When cleared to 0, bytes from register addresses 0 and 1, 2 and 3, etc (even, then odd register addresses) are paired to form a word. When set to 1, bytes from register addresses are paired 1 and 2, 3 and 4, etc. (odd, then even register addresses) are paired to form a word.

I2C_SLV1_CTRL @ 0x2A

I2C_SLV1_LEN [3:0]

The number of bytes transferred is specified by I2C_SLV1_LEN. When more than 1 byte is transferred (I2C_SLV1_LEN > 1), data is read from (written to) sequential addresses starting from I2C_SLV1_REG.

I2C Slave 2 Address (I2C_SLV2_ADDR @ 0x2B)

Register Bitfields

• [7] I2C_SLV2_RW
• [6:0] I2C_SLV2_ADDR

Configures the device address and data transfer mode for Slave 2. I2C data transactions are performed at the Sample Rate, as defined in Register 25. The user is responsible for ensuring that I2C data transactions to and from each enabled Slave can be completed within a single period of the Sample Rate.The I2C slave access rate can be reduced relative to the Sample Rate. This reduced access rate is determined by I2C_MST_DLY (Register 52). Whether a slave’s access rate is reduced relative to the Sample Rate is determined by I2C_MST_DELAY_CTRL (Register 103).The processing order for the slaves is fixed. The sequence followed for processing the slaves is Slave 0, Slave 1, Slave 2, Slave 3 and Slave 4. If a particular Slave is disabled it will be skipped.Each slave can either be accessed at the sample rate or at a reduced sample rate. In a case where some slaves are accessed at the Sample Rate and some slaves are accessed at the reduced rate, the sequence of accessing the slaves (Slave 0 to Slave 4) is still followed. However, the reduced rate slaves will be skipped if their access rate dictates that they should not be accessed during that particular cycle. For further information regarding the reduced access rate, please refer to Register 52. Whether a slave is accessed at the Sample Rate or at the reduced rate is determined by the Delay Enable bits in Register 103.

I2C_SLV2_ADDR @ 0x2B

I2C_SLV2_RW [7]

I2C slave data transactions between the MPU-60X0 and Slave 2 are set as either read or write operations by the I2C_SLV2_RW bit. When this bit is 1, the transfer is a read operation. When the bit is 0, the transfer is a write operation.In read mode, the result of the read is placed in the lowest available EXT_SENS_DATA register. For further information regarding the allocation of read results, please refer to the EXT_SENS_DATA register description (Registers 73 – 96). In write mode, the contents of I2C_SLV2_DO (Register 99) will be written to the slave device.

I2C_SLV2_ADDR @ 0x2B

I2C_SLV2_ADDR [6:0]

Specifies the 7-bit I2C slave address of Slave 2.

I2C Slave 2 Register (I2C_SLV2_REG @ 0x2C)

Register Bitfields

• [7:0] I2C_SLV2_REG

I2C_SLV2_REG @ 0x2C

I2C_SLV2_REG [7:0]

Specifies the internal register at which to begin data transfer within Slave 2.

I2C Slave 2 Control (I2C_SLV2_CTRL @ 0x2D)

Register Bitfields

• [7] I2C_SLV2_EN
• [6] I2C_SLV2_BYTE_SW
• [5] I2C_SLV2_REG_DIS
• [4] I2C_SLV2_GRP
• [3:0] I2C_SLV2_LEN

I2C_SLV2_CTRL @ 0x2D

I2C_SLV2_EN [7]

Enables Slave 2 for I2C data transaction. A data transaction is performed only if more than zero bytes are to be transferred (I2C_SLV2_LEN > 0) between an enabled slave device (I2C_SLV2_EN = 1).

I2C_SLV2_CTRL @ 0x2D

I2C_SLV2_BYTE_SW [6]

Configures byte swapping of word pairs. When byte swapping is enabled, the high and low bytes of a word pair are swapped. Please refer to I2C_SLV2_GRP for the pairing convention of the word pairs. When this bit is cleared to 0, bytes transferred to and from Slave 2 will be written to EXT_SENS_DATA registers in the order they were transferred.

I2C_SLV2_CTRL @ 0x2D

I2C_SLV2_REG_DIS [5]

Disable slave register address sending. When set to 1, the transaction will read or write data only. When cleared to 0, the transaction will write a register address prior to reading or writing data. This bit should equal 0 when specifying the register address within the Slave device to/from which the ensuing data transaction will take place.

I2C_SLV2_CTRL @ 0x2D

I2C_SLV2_GRP [4]

Specifies the grouping order of word pairs received from registers. When cleared to 0, bytes from register addresses 0 and 1, 2 and 3, etc (even, then odd register addresses) are paired to form a word. When set to 1, bytes from register addresses are paired 1 and 2, 3 and 4, etc. (odd, then even register addresses) are paired to form a word.

I2C_SLV2_CTRL @ 0x2D

I2C_SLV2_LEN [3:0]

The number of bytes transferred is specified by I2C_SLV2_LEN. When more than 1 byte is transferred (I2C_SLV2_LEN > 1), data is read from (written to) sequential addresses starting from I2C_SLV2_REG.

I2C Slave 3 Address (I2C_SLV3_ADDR @ 0x2E)

Register Bitfields

• [7] I2C_SLV3_RW
• [6:0] I2C_SLV3_ADDR

Configures the device address and data transfer mode for Slave 3. I2C data transactions are performed at the Sample Rate, as defined in Register 25. The user is responsible for ensuring that I2C data transactions to and from each enabled Slave can be completed within a single period of the Sample Rate.The I2C slave access rate can be reduced relative to the Sample Rate. This reduced access rate is determined by I2C_MST_DLY (Register 52). Whether a slave’s access rate is reduced relative to the Sample Rate is determined by I2C_MST_DELAY_CTRL (Register 103).The processing order for the slaves is fixed. The sequence followed for processing the slaves is Slave 0, Slave 1, Slave 2, Slave 3 and Slave 4. If a particular Slave is disabled it will be skipped.Each slave can either be accessed at the sample rate or at a reduced sample rate. In a case where some slaves are accessed at the Sample Rate and some slaves are accessed at the reduced rate, the sequence of accessing the slaves (Slave 0 to Slave 4) is still followed. However, the reduced rate slaves will be skipped if their access rate dictates that they should not be accessed during that particular cycle. For further information regarding the reduced access rate, please refer to Register 52. Whether a slave is accessed at the Sample Rate or at the reduced rate is determined by the Delay Enable bits in Register 103.

I2C_SLV3_ADDR @ 0x2E

I2C_SLV3_RW [7]

I2C slave data transactions between the MPU-60X0 and Slave 3 are set as either read or write operations by the I2C_SLV3_RW bit. When this bit is 1, the transfer is a read operation. When the bit is 0, the transfer is a write operation.In read mode, the result of the read is placed in the lowest available EXT_SENS_DATA register. For further information regarding the allocation of read results, please refer to the EXT_SENS_DATA register description (Registers 73 – 96). In write mode, the contents of I2C_SLV3_DO (Register 99) will be written to the slave device.

I2C_SLV3_ADDR @ 0x2E

I2C_SLV3_ADDR [6:0]

Specifies the 7-bit I2C slave address of Slave 3.

I2C Slave 3 Register (I2C_SLV3_REG @ 0x2F)

Register Bitfields

• [7:0] I2C_SLV3_REG

I2C_SLV3_REG @ 0x2F

I2C_SLV3_REG [7:0]

Specifies the internal register at which to begin data transfer within Slave 3.

I2C Slave 3 Control (I2C_SLV3_CTRL @ 0x30)

Register Bitfields

• [7] I2C_SLV3_EN
• [6] I2C_SLV3_BYTE_SW
• [5] I2C_SLV3_REG_DIS
• [4] I2C_SLV3_GRP
• [3:0] I2C_SLV3_LEN

I2C_SLV3_CTRL @ 0x30

I2C_SLV3_EN [7]

Enables Slave 3 for I2C data transaction. A data transaction is performed only if more than zero bytes are to be transferred (I2C_SLV3_LEN > 0) between an enabled slave device (I2C_SLV3_EN = 1).

I2C_SLV3_CTRL @ 0x30

I2C_SLV3_BYTE_SW [6]

Configures byte swapping of word pairs. When byte swapping is enabled, the high and low bytes of a word pair are swapped. Please refer to I2C_SLV3_GRP for the pairing convention of the word pairs. When this bit is cleared to 0, bytes transferred to and from Slave 3 will be written to EXT_SENS_DATA registers in the order they were transferred.

I2C_SLV3_CTRL @ 0x30

I2C_SLV3_REG_DIS [5]

Disable slave register address sending. When set to 1, the transaction will read or write data only. When cleared to 0, the transaction will write a register address prior to reading or writing data. This bit should equal 0 when specifying the register address within the Slave device to/from which the ensuing data transaction will take place.

I2C_SLV3_CTRL @ 0x30

I2C_SLV3_GRP [4]

Specifies the grouping order of word pairs received from registers. When cleared to 0, bytes from register addresses 0 and 1, 2 and 3, etc (even, then odd register addresses) are paired to form a word. When set to 1, bytes from register addresses are paired 1 and 2, 3 and 4, etc. (odd, then even register addresses) are paired to form a word.

I2C_SLV3_CTRL @ 0x30

I2C_SLV3_LEN [3:0]

The number of bytes transferred is specified by I2C_SLV3_LEN. When more than 1 byte is transferred (I2C_SLV3_LEN > 1), data is read from (written to) sequential addresses starting from I2C_SLV3_REG.

I2C Slave 4 Address (I2C_SLV4_ADDR @ 0x31)

Register Bitfields

• [7] I2C_SLV4_RW
• [6:0] I2C_SLV4_ADDR

Configures the device address and data transfer mode for Slave 4. I2C data transactions are performed at the Sample Rate, as defined in Register 25. The user is responsible for ensuring that I2C data transactions to and from each enabled Slave can be completed within a single period of the Sample Rate.The I2C slave access rate can be reduced relative to the Sample Rate. This reduced access rate is determined by I2C_MST_DLY (Register 52). Whether a slave’s access rate is reduced relative to the Sample Rate is determined by I2C_MST_DELAY_CTRL (Register 103).The processing order for the slaves is fixed. The sequence followed for processing the slaves is Slave 0, Slave 1, Slave 2, Slave 3 and Slave 4. If a particular Slave is disabled it will be skipped.Each slave can either be accessed at the sample rate or at a reduced sample rate. In a case where some slaves are accessed at the Sample Rate and some slaves are accessed at the reduced rate, the sequence of accessing the slaves (Slave 0 to Slave 4) is still followed. However, the reduced rate slaves will be skipped if their access rate dictates that they should not be accessed during that particular cycle. For further information regarding the reduced access rate, please refer to Register 52. Whether a slave is accessed at the Sample Rate or at the reduced rate is determined by the Delay Enable bits in Register 103.

I2C_SLV4_ADDR @ 0x31

I2C_SLV4_RW [7]

I2C slave data transactions between the MPU-60X0 and Slave 4 are set as either read or write operations by the I2C_SLV4_RW bit. When this bit is 1, the transfer is a read operation. When the bit is 0, the transfer is a write operation.In read mode, the result of the read will be available in I2C_SLV4_DI. In write mode, the contents of I2C_SLV4_DO will be written into the slave device. A data transaction is performed only if the I2C_SLV4_EN bit is set to 1. The data transaction should be enabled once its parameters are configured in the _ADDR and _REG registers. For write, the _DO register is also required. I2C_SLV4_EN will be cleared after the transaction is performed once.An interrupt is triggered at the completion of a Slave 4 data transaction if the interrupt is enabled. The status of this interrupt can be observed in Register 54.

I2C_SLV4_ADDR @ 0x31

I2C_SLV4_ADDR [6:0]

Specifies the 7-bit I2C slave address of Slave 4.

I2C Slave 4 Register (I2C_SLV4_REG @ 0x32)

Register Bitfields

• [7:0] I2C_SLV4_REG

I2C_SLV4_REG @ 0x32

I2C_SLV4_REG [7:0]

Specifies the internal register at which to begin data transfer within Slave 4.

I2C Slave 4 Data Output (I2C_SLV4_DO @ 0x33)

Register Bitfields

• [7:0] I2C_SLV4_DO

I2C_SLV4_DO @ 0x33

I2C_SLV4_DO [7:0]

This register stores the data to be written into the Slave 4. If I2C_SLV4_RW is set 1 (set to read), this register has no effect.

I2C Slave 4 Control (I2C_SLV4_CTRL @ 0x34)

Register Bitfields

• [7] I2C_SLV4_EN
• [6] I2C_SLV4_INT_EN
• [5] I2C_SLV4_REG_DIS
• [4:0] I2C_MST_DLY

I2C_SLV4_CTRL @ 0x34

I2C_SLV4_EN [7]

Enables Slave 4 for I2C data transaction. A data transaction is performed only if the I2C_SLV4_EN bit is set to 1. The data transaction should be enabled once its parameters are configured in the _ADDR and _REG registers. For write, the _DO register is also required. I2C_SLV4_EN will be cleared after the transaction is performed once.

I2C_SLV4_CTRL @ 0x34

I2C_SLV4_INT_EN [6]

When set to 1, this bit enables the generation of an interrupt signal upon completion of a Slave 4 transaction. When cleared to 0, this bit disables the generation of an interrupt signal upon completion of a Slave 4 transaction.The interrupt status can be observed in Register 54.

I2C_SLV4_CTRL @ 0x34

I2C_SLV4_REG_DIS [5]

Disable slave register address sending. When I2C_SLV4_REG_DIS is set to 1, the transaction will read or write data instead of writing a register address. This bit should equal 0 when specifying the register address within the Slave device to/from which the ensuing data transaction will take place.

I2C_SLV4_CTRL @ 0x34

I2C_MST_DLY [4:0]

I2C_MST_DLY configures the reduced access rate of I2C slaves relative to the Sample Rate. When a slave’s access rate is decreased relative to the Sample Rate, the slave is accessed every:1 / (1 + I2C_MST_DLY) samplesThis base Sample Rate in turn is determined by SMPLRT_DIV (register 25) and DLPF_CFG (register 26). Whether a slave’s access rate is reduced relative to the Sample Rate is determined by I2C_MST_DELAY_CTRL (register 103).

I2C Slave 4 Data Input (I2C_SLV4_DI @ 0x35)

Register Bitfields

• [7:0] I2C_SLV4_DI

I2C_SLV4_DI @ 0x35

I2C_SLV4_DI [7:0]

This register stores the data read from Slave 4. This field is populated after a read transaction.

I2C Master Status (I2C_MST_STATUS @ 0x36)

Register Bitfields

• [7] PASS_THROUGH
• [6] I2C_SLV4_DONE
• [5] I2C_LOST_ARB
• [4] I2C_SLV4_NACK
• [3] I2C_SLV3_NACK
• [2] I2C_SLV2_NACK
• [1] I2C_SLV1_NACK
• [0] I2C_SLV0_NACK

This register shows the status of the interrupt generating signals in the I2C Master within the MPU-60X0. This register also communicates the status of the FSYNC interrupt to the host processor.Reading this register will clear all the status bits in the register.

I2C_MST_STATUS @ 0x36

PASS_THROUGH [7]

This bit reflects the status of the FSYNC interrupt from an external device into the MPU-60X0. This is used as a way to pass an external interrupt through the MPU-60X0 to the host application processor. When set to 1, this bit will cause an interrupt if FSYNC_INT_EN is asserted in INT_PIN_CFG (Register 55).

I2C_MST_STATUS @ 0x36

I2C_SLV4_DONE [6]

Automatically sets to 1 when a Slave 4 transaction has completed. This triggers an interrupt if the I2C_MST_INT_EN bit in the INT_ENABLE register (Register 56) is asserted and if the SLV_4_DONE_INT bit is asserted in the I2C_SLV4_CTRL register (Register 52).

I2C_MST_STATUS @ 0x36

I2C_LOST_ARB [5]

This bit automatically sets to 1 when the I2C Master has lost arbitration of the auxiliary I2C bus (an error condition). This triggers an interrupt if the I2C_MST_INT_EN bit in the INT_ENABLE register (Register 56) is asserted.

I2C_MST_STATUS @ 0x36

I2C_SLV4_NACK [4]

This bit automatically sets to 1 when the I2C Master receives a NACK in a transaction with Slave 4. This triggers an interrupt if the I2C_MST_INT_EN bit in the INT_ENABLE register (Register 56) is asserted.

I2C_MST_STATUS @ 0x36

I2C_SLV3_NACK [3]

This bit automatically sets to 1 when the I2C Master receives a NACK in a transaction with Slave 3. This triggers an interrupt if the I2C_MST_INT_EN bit in the INT_ENABLE register (Register 56) is asserted.

I2C_MST_STATUS @ 0x36

I2C_SLV2_NACK [2]

This bit automatically sets to 1 when the I2C Master receives a NACK in a transaction with Slave 2. This triggers an interrupt if the I2C_MST_INT_EN bit in the INT_ENABLE register (Register 56) is asserted.

I2C_MST_STATUS @ 0x36

I2C_SLV1_NACK [1]

This bit automatically sets to 1 when the I2C Master receives a NACK in a transaction with Slave 1. This triggers an interrupt if the I2C_MST_INT_EN bit in the INT_ENABLE register (Register 56) is asserted.

I2C_MST_STATUS @ 0x36

I2C_SLV0_NACK [0]

This bit automatically sets to 1 when the I2C Master receives a NACK in a transaction with Slave 0. This triggers an interrupt if the I2C_MST_INT_EN bit in the INT_ENABLE register (Register 56) is asserted.

INT Pin / Bypass Enable Configuration (INT_PIN_CFG @ 0x37)

Register Bitfields

• [7] INT_LEVEL
• [6] INT_OPEN
• [5] LATCH_INT_EN
• [4] INT_RD_CLEAR
• [3] FSYNC_INT_LEVEL
• [2] FSYNC_INT_EN
• [1] I2C_BYPASS_EN
• [0] CLKOUT_EN

This register configures the behavior of the interrupt signals at the INT pins. This register is also used to enable the FSYNC Pin to be used as an interrupt to the host application processor, as well as to enable Bypass Mode on the I2C Master. This bit also enables the clock output.

INT_PIN_CFG @ 0x37

INT_LEVEL [7]

Configures interrupt pin logic level. When this bit is equal to 0, the logic level for the INT pin is active high. When this bit is equal to 1, the logic level for the INT pin is active low.

INT_PIN_CFG @ 0x37

INT_OPEN [6]

Configures interrupt pin drive type. When this bit is equal to 0, the INT pin is configured as push-pull. When this bit is equal to 1, the INT pin is configured as open drain.

INT_PIN_CFG @ 0x37

LATCH_INT_EN [5]

Configures interrupt latch mode. When this bit is equal to 0, the INT pin emits a 50us long pulse. When this bit is equal to 1, the INT pin is held high until the interrupt is cleared.

INT_PIN_CFG @ 0x37

INT_RD_CLEAR [4]

Configures interrupt read clear mode. When this bit is equal to 0, interrupt status bits are cleared only by reading INT_STATUS (Register 58). When this bit is equal to 1, interrupt status bits are cleared on any read operation.

INT_PIN_CFG @ 0x37

FSYNC_INT_LEVEL [3]

Configures FSYNC pin logic level. When this bit is equal to 0, the logic level for the FSYNC pin (when used as an interrupt to the host processor) is active high. When this bit is equal to 1, the logic level for the FSYNC pin (when used as an interrupt to the host processor) is active low.

INT_PIN_CFG @ 0x37

FSYNC_INT_EN [2]

FSYNC_INT_EN enables the FSYNC pin to be used as an interrupt to the host application processor. A transition to the active level specified in FSYNC_INT_LEVEL will trigger an interrupt. The status of this interrupt is read from the PASS_THROUGH bit in the I2C Master Status Register (Register 54).When equal to 0, this bit disables the FSYNC pin from causing an interrupt to the host processor. When equal to 1, this bit enables the FSYNC pin to be used as an interrupt to the host processor.

INT_PIN_CFG @ 0x37

I2C_BYPASS_EN [1]

When I2C_BYPASS_EN is equal to 1 and I2C_MST_EN (Register 106 bit[5]) is equal to 0, the host application processor will be able to directly access the auxiliary I2C bus of the MPU-60X0. When this bit is equal to 0, the host application processor will not be able to directly access the auxiliary I2C bus of the MPU-60X0 regardless of the state of I2C_MST_EN.

INT_PIN_CFG @ 0x37

CLKOUT_EN [0]

When this bit is equal to 1, a reference clock output is provided at the CLKOUT pin. When this bit is equal to 0, the clock output is disabled.For further information regarding CLKOUT, please refer to the MPU-60X0 Product Specification document.

INT_ENABLE @ 0x38

Register Bitfields

• [7] FF_EN
• [6] MOT_EN
• [5] ZMOT_EN
• [4] FIFO_OFLOW_EN
• [3] I2C_MST_INT_EN
• [2] PLL_RDY_INT_EN
• [1] DMP_INT_EN
• [0] RAW_RDY_EN

This register enables interrupt generation by interrupt sources.For information regarding Free Fall detection, Motion detection, and Zero Motion detection, please refer to Registers 29 to 34. For information regarding the interrupt status for of each interrupt generation source, please refer to Register 58. Further information regarding I2C Master interrupt generation can be found in Register 54.

INT_ENABLE @ 0x38

FF_EN [7]

When set to 1, this bit enables Free Fall detection to generate an interrupt.

INT_ENABLE @ 0x38

MOT_EN [6]

When set to 1, this bit enables Motion detection to generate an interrupt.

INT_ENABLE @ 0x38

ZMOT_EN [5]

When set to 1, this bit enables Zero Motion detection to generate an interrupt.

INT_ENABLE @ 0x38

FIFO_OFLOW_EN [4]

When set to 1, this bit enables a FIFO buffer overflow to generate an interrupt.

INT_ENABLE @ 0x38

I2C_MST_INT_EN [3]

When set to 1, this bit enables any of the I2C Master interrupt sources to generate an interrupt.

INT_ENABLE @ 0x38

DMP_INT_EN [1]

When set to 1, this bit enables DMP-related interrupts.

INT_ENABLE @ 0x38

RAW_RDY_EN [0]

When set to 1, this bit enables the Data Ready interrupt, which occurs each time a write operation to all of the sensor registers has been completed.

INT_STATUS @ 0x3A

Register Bitfields

• [7] FF_INT
• [6] MOT_INT
• [5] ZMOT_INT
• [4] FIFO_OFLOW_INT
• [3] I2C_MST_INT
• [2] PLL_RDY_INT
• [1] DMP_INT
• [0] RAW_RDY_INT

This register shows the interrupt status of each interrupt generation source. Each bit will clear after the register is read.For information regarding the corresponding interrupt enable bits, please refer to Register 56. For a list of I2C Master interrupts, please refer to Register 54.

INT_STATUS @ 0x3A

FF_INT [7]

This bit automatically sets to 1 when a Free Fall interrupt has been generated. The bit clears to 0 after the register has been read.

INT_STATUS @ 0x3A

MOT_INT [6]

This bit automatically sets to 1 when a Motion Detection interrupt has been generated. The bit clears to 0 after the register has been read.

INT_STATUS @ 0x3A

ZMOT_INT [5]

This bit automatically sets to 1 when a Zero Motion Detection interrupt has been generated. The bit clears to 0 after the register has been read.

INT_STATUS @ 0x3A

FIFO_OFLOW_INT [4]

This bit automatically sets to 1 when a FIFO buffer overflow interrupt has been generated. The bit clears to 0 after the register has been read.

INT_STATUS @ 0x3A

I2C_MST_INT [3]

This bit automatically sets to 1 when an I2C Master interrupt has been generated. For a list of I2C Master interrupts, please refer to Register 54. The bit clears to 0 after the register has been read.

INT_STATUS @ 0x3A

DMP_INT [1]

This bit automatically sets to 1 when a DMP interrupt is generated. The bit clears to 0 after the register has been read. More specific DMP interrupt flags are contained in the DMP_INT_STATUS register (0x39).

INT_STATUS @ 0x3A

RAW_RDY_INT [0]

This bit automatically sets to 1 when a Data Ready interrupt is generated. The bit clears to 0 after the register has been read.

ACCEL_XOUT_H @ 0x3B

Register Bitfields

• [15:0] ACCEL_XOUT

These registers store the most recent accelerometer measurements. Accelerometer measurements are written to these registers at the Sample Rate as defined in Register 25.The accelerometer measurement registers, along with the temperature measurement registers, gyroscope measurement registers, and external sensor data registers, are composed of two sets of registers: an internal register set and a user-facing read register set.The data within the accelerometer sensors’ internal register set is always updated at the Sample Rate. Meanwhile, the user-facing read register set duplicates the internal register set’s data values whenever the serial interface is idle. This guarantees that a burst read of sensor registers will read measurements from the same sampling instant. Note that if burst reads are not used, the user is responsible for ensuring a set of single byte reads correspond to a single sampling instant by checking the Data Ready interrupt.Each 16-bit accelerometer measurement has a full scale defined in ACCEL_FS (Register 28). For each full scale setting, the accelerometers’ sensitivity per LSB in ACCEL_xOUT is shown in the table below.AFS_SEL Full Scale Range LSB Sensitivity0 ±2g 16384 LSB/mg1 ±4g 8192 LSB/mg2 ±8g 4096 LSB/mg3 ±16g 2048 LSB/mg

ACCEL_XOUT_H @ 0x3B

ACCEL_XOUT [15:0]

16-bit 2’s complement value. Stores the most recent X axis accelerometer measurement.

ACCEL_XOUT_L @ 0x3C

These registers store the most recent accelerometer measurements. Accelerometer measurements are written to these registers at the Sample Rate as defined in Register 25. See ACCEL_XOUT_H for more details.

ACCEL_YOUT_H @ 0x3D

Register Bitfields

• [15:0] ACCEL_YOUT

These registers store the most recent accelerometer measurements. Accelerometer measurements are written to these registers at the Sample Rate as defined in Register 25. See ACCEL_XOUT_H for more details.

ACCEL_YOUT_H @ 0x3D

ACCEL_YOUT [15:0]

16-bit 2’s complement value. Stores the most recent Y axis accelerometer measurement.

ACCEL_YOUT_L @ 0x3E

These registers store the most recent accelerometer measurements. Accelerometer measurements are written to these registers at the Sample Rate as defined in Register 25. See ACCEL_XOUT_H for more details.

ACCEL_ZOUT_H @ 0x3F

Register Bitfields

• [15:0] ACCEL_ZOUT

These registers store the most recent accelerometer measurements. Accelerometer measurements are written to these registers at the Sample Rate as defined in Register 25. See ACCEL_XOUT_H for more details.

ACCEL_ZOUT_H @ 0x3F

ACCEL_ZOUT [15:0]

16-bit 2’s complement value. Stores the most recent Z axis accelerometer measurement.

ACCEL_ZOUT_L @ 0x40

These registers store the most recent accelerometer measurements. Accelerometer measurements are written to these registers at the Sample Rate as defined in Register 25. See ACCEL_XOUT_H for more details.

TEMP_OUT_H @ 0x41

Register Bitfields

• [15:0] TEMP_OUT

These registers store the most recent temperature sensor measurement. Temperature measurements are written to these registers at the Sample Rate as defined in Register 25.These temperature measurement registers, along with the accelerometer measurement registers, gyroscope measurement registers, and external sensor data registers, are composed of two sets of registers: an internal register set and a user-facing read register set.The data within the temperature sensor’s internal register set is always updated at the Sample Rate. Meanwhile, the user-facing read register set duplicates the internal register set’s data values whenever the serial interface is idle. This guarantees that a burst read of sensor registers will read measurements from the same sampling instant. Note that if burst reads are not used, the user is responsible for ensuring a set of single byte reads correspond to a single sampling instant by checking the Data Ready interrupt.

TEMP_OUT_H @ 0x41

TEMP_OUT [15:0]

16-bit signed value. Stores the most recent temperature sensor measurement.

TEMP_OUT_L @ 0x42

These registers store the most recent temperature sensor measurement. Temperature measurements are written to these registers at the Sample Rate as defined in Register 25. See TEMP_OUT_H for more details.

GYRO_XOUT_H @ 0x43

Register Bitfields

• [15:0] GYRO_XOUT

These registers store the most recent gyroscope measurements. Gyroscope measurements are written to these registers at the Sample Rate as defined in Register 25.These gyroscope measurement registers, along with the accelerometer measurement registers, temperature measurement registers, and external sensor data registers, are composed of two sets of registers: an internal register set and a user-facing read register set.The data within the gyroscope sensors’ internal register set is always updated at the Sample Rate. Meanwhile, the user-facing read register set duplicates the internal register set’s data values whenever the serial interface is idle. This guarantees that a burst read of sensor registers will read measurements from the same sampling instant. Note that if burst reads are not used, the user is responsible for ensuring a set of single byte reads correspond to a single sampling instant by checking the Data Ready interrupt.Each 16-bit gyroscope measurement has a full scale defined in FS_SEL (Register 27). For each full scale setting, the gyroscopes’ sensitivity per LSB in GYRO_xOUT is shown in the table below:FS_SEL Full Scale Range LSB Sensitivity0 ± 250 °/s 131 LSB/°/s1 ± 500 °/s 65.5 LSB/°/s2 ± 1000 °/s 32.8 LSB/°/s3 ± 2000 °/s 16.4 LSB/°/s

GYRO_XOUT_H @ 0x43

GYRO_XOUT [15:0]

16-bit 2’s complement value. Stores the most recent X axis gyroscope measurement.

GYRO_XOUT_L @ 0x44

These registers store the most recent gyroscope measurements. Gyroscope measurements are written to these registers at the Sample Rate as defined in Register 25. See GYRO_XOUT_H for more details.

GYRO_YOUT_H @ 0x45

Register Bitfields

• [15:0] GYRO_YOUT

These registers store the most recent gyroscope measurements. Gyroscope measurements are written to these registers at the Sample Rate as defined in Register 25. See GYRO_XOUT_H for more details.

GYRO_YOUT_H @ 0x45

GYRO_YOUT [15:0]

16-bit 2’s complement value. Stores the most recent Y axis gyroscope measurement.

GYRO_YOUT_L @ 0x46

These registers store the most recent gyroscope measurements. Gyroscope measurements are written to these registers at the Sample Rate as defined in Register 25. See GYRO_XOUT_H for more details.

GYRO_ZOUT_H @ 0x47

Register Bitfields

• [15:0] GYRO_ZOUT

These registers store the most recent gyroscope measurements. Gyroscope measurements are written to these registers at the Sample Rate as defined in Register 25. See GYRO_XOUT_H for more details.

GYRO_ZOUT_H @ 0x47

GYRO_ZOUT [15:0]

16-bit 2’s complement value. Stores the most recent Z axis gyroscope measurement.

GYRO_ZOUT_L @ 0x48

These registers store the most recent gyroscope measurements. Gyroscope measurements are written to these registers at the Sample Rate as defined in Register 25. See GYRO_XOUT_H for more details.

EXT_SENS_DATA_00 @ 0x49

Register Bitfields

• [7:0] EXT_SENS_DATA_00

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53).External sensor data is written to these registers at the Sample Rate as defined in Register 25. This access rate can be reduced by using the Slave Delay Enable registers (Register 103).External sensor data registers, along with the gyroscope measurement registers, accelerometer measurement registers, and temperature measurement registers, are composed of two sets of registers: an internal register set and a user-facing read register set.The data within the external sensors’ internal register set is always updated at the Sample Rate (or the reduced access rate) whenever the serial interface is idle. This guarantees that a burst read of sensor registers will read measurements from the same sampling instant. Note that if burst reads are not used, the user is responsible for ensuring a set of single byte reads correspond to a single sampling instant by checking the Data Ready interrupt.Data is placed in these external sensor data registers according to I2C_SLV0_CTRL, I2C_SLV1_CTRL, I2C_SLV2_CTRL, and I2C_SLV3_CTRL (Registers 39, 42, 45, and 48). When more than zero bytes are read (I2C_SLVx_LEN > 0) from an enabled slave (I2C_SLVx_EN = 1), the slave is read at the Sample Rate (as defined in Register 25) or delayed rate (if specified in Register 52 and 103). During each Sample cycle, slave reads are performed in order of Slave number. If all slaves are enabled with more than zero bytes to be read, the order will be Slave 0, followed by Slave 1, Slave 2, and Slave 3.Each enabled slave will have EXT_SENS_DATA registers associated with it by number of bytes read (I2C_SLVx_LEN) in order of slave number, starting from EXT_SENS_DATA_00. Note that this means enabling or disabling a slave may change the higher numbered slaves’ associated registers. Furthermore, if fewer total bytes are being read from the external sensors as a result of such a change, then the data remaining in the registers which no longer have an associated slave device (i.e. high numbered registers) will remain in these previously allocated registers unless reset.If the sum of the read lengths of all SLVx transactions exceed the number of available EXT_SENS_DATA registers, the excess bytes will be dropped. There are 24 EXT_SENS_DATA registers and hence the total read lengths between all the slaves cannot be greater than 24 or some bytes will be lost.Note: Slave 4’s behavior is distinct from that of Slaves 0-3. For further information regarding the characteristics of Slave 4, please refer to Registers 49 to 53.Example:Suppose that Slave 0 is enabled with 4 bytes to be read (I2C_SLV0_EN = 1 and I2C_SLV0_LEN = 4) while Slave 1 is enabled with 2 bytes to be read, (I2C_SLV1_EN=1 and I2C_SLV1_LEN = 2). In such a situation, EXT_SENS_DATA _00 through _03 will be associated with Slave 0, while EXT_SENS_DATA _04 and 05 will be associated with Slave 1.If Slave 2 is enabled as well, registers starting from EXT_SENS_DATA_06 will be allocated to Slave 2.If Slave 2 is disabled while Slave 3 is enabled in this same situation, then registers starting from EXT_SENS_DATA_06 will be allocated to Slave 3 instead.Register Allocation for Dynamic Disable vs. Normal DisableIf a slave is disabled at any time, the space initially allocated to the slave in the EXT_SENS_DATA register, will remain associated with that slave. This is to avoid dynamic adjustment of the register allocation.The allocation of the EXT_SENS_DATA registers is recomputed only when (1) all slaves are disabled, or (2) the I2C_MST_RST bit is set (Register 106) .This above is also true if one of the slaves gets NACKed and stops functioning.

EXT_SENS_DATA_00 @ 0x49

EXT_SENS_DATA_00 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53).External sensor data is written to these registers at the Sample Rate as defined in Register 25. This access rate can be reduced by using the Slave Delay Enable registers (Register 103).External sensor data registers, along with the gyroscope measurement registers, accelerometer measurement registers, and temperature measurement registers, are composed of two sets of registers: an internal register set and a user-facing read register set.The data within the external sensors’ internal register set is always updated at the Sample Rate (or the reduced access rate) whenever the serial interface is idle. This guarantees that a burst read of sensor registers will read measurements from the same sampling instant. Note that if burst reads are not used, the user is responsible for ensuring a set of single byte reads correspond to a single sampling instant by checking the Data Ready interrupt.Data is placed in these external sensor data registers according to I2C_SLV0_CTRL, I2C_SLV1_CTRL, I2C_SLV2_CTRL, and I2C_SLV3_CTRL (Registers 39, 42, 45, and 48). When more than zero bytes are read (I2C_SLVx_LEN > 0) from an enabled slave (I2C_SLVx_EN = 1), the slave is read at the Sample Rate (as defined in Register 25) or delayed rate (if specified in Register 52 and 103). During each Sample cycle, slave reads are performed in order of Slave number. If all slaves are enabled with more than zero bytes to be read, the order will be Slave 0, followed by Slave 1, Slave 2, and Slave 3.Each enabled slave will have EXT_SENS_DATA registers associated with it by number of bytes read (I2C_SLVx_LEN) in order of slave number, starting from EXT_SENS_DATA_00. Note that this means enabling or disabling a slave may change the higher numbered slaves’ associated registers. Furthermore, if fewer total bytes are being read from the external sensors as a result of such a change, then the data remaining in the registers which no longer have an associated slave device (i.e. high numbered registers) will remain in these previously allocated registers unless reset.If the sum of the read lengths of all SLVx transactions exceed the number of available EXT_SENS_DATA registers, the excess bytes will be dropped. There are 24 EXT_SENS_DATA registers and hence the total read lengths between all the slaves cannot be greater than 24 or some bytes will be lost.Note: Slave 4’s behavior is distinct from that of Slaves 0-3. For further information regarding the characteristics of Slave 4, please refer to Registers 49 to 53.Example:Suppose that Slave 0 is enabled with 4 bytes to be read (I2C_SLV0_EN = 1 and I2C_SLV0_LEN = 4) while Slave 1 is enabled with 2 bytes to be read, (I2C_SLV1_EN=1 and I2C_SLV1_LEN = 2). In such a situation, EXT_SENS_DATA _00 through _03 will be associated with Slave 0, while EXT_SENS_DATA _04 and 05 will be associated with Slave 1.If Slave 2 is enabled as well, registers starting from EXT_SENS_DATA_06 will be allocated to Slave 2.If Slave 2 is disabled while Slave 3 is enabled in this same situation, then registers starting from EXT_SENS_DATA_06 will be allocated to Slave 3 instead.Register Allocation for Dynamic Disable vs. Normal DisableIf a slave is disabled at any time, the space initially allocated to the slave in the EXT_SENS_DATA register, will remain associated with that slave. This is to avoid dynamic adjustment of the register allocation.The allocation of the EXT_SENS_DATA registers is recomputed only when (1) all slaves are disabled, or (2) the I2C_MST_RST bit is set (Register 106) .This above is also true if one of the slaves gets NACKed and stops functioning.

EXT_SENS_DATA_01 @ 0x4A

Register Bitfields

• [7:0] EXT_SENS_DATA_01

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_01 @ 0x4A

EXT_SENS_DATA_01 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_02 @ 0x4B

Register Bitfields

• [7:0] EXT_SENS_DATA_02

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_02 @ 0x4B

EXT_SENS_DATA_02 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_03 @ 0x4C

Register Bitfields

• [7:0] EXT_SENS_DATA_03

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_03 @ 0x4C

EXT_SENS_DATA_03 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_04 @ 0x4D

Register Bitfields

• [7:0] EXT_SENS_DATA_04

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_04 @ 0x4D

EXT_SENS_DATA_04 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_05 @ 0x4E

Register Bitfields

• [7:0] EXT_SENS_DATA_05

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_05 @ 0x4E

EXT_SENS_DATA_05 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_06 @ 0x4F

Register Bitfields

• [7:0] EXT_SENS_DATA_06

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_06 @ 0x4F

EXT_SENS_DATA_06 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_07 @ 0x50

Register Bitfields

• [7:0] EXT_SENS_DATA_07

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_07 @ 0x50

EXT_SENS_DATA_07 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_08 @ 0x51

Register Bitfields

• [7:0] EXT_SENS_DATA_08

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_08 @ 0x51

EXT_SENS_DATA_08 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_09 @ 0x52

Register Bitfields

• [7:0] EXT_SENS_DATA_09

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_09 @ 0x52

EXT_SENS_DATA_09 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_10 @ 0x53

Register Bitfields

• [7:0] EXT_SENS_DATA_10

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_10 @ 0x53

EXT_SENS_DATA_10 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_11 @ 0x54

Register Bitfields

• [7:0] EXT_SENS_DATA_11

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_11 @ 0x54

EXT_SENS_DATA_11 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_12 @ 0x55

Register Bitfields

• [7:0] EXT_SENS_DATA_12

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_12 @ 0x55

EXT_SENS_DATA_12 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_13 @ 0x56

Register Bitfields

• [7:0] EXT_SENS_DATA_13

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_13 @ 0x56

EXT_SENS_DATA_13 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_14 @ 0x57

Register Bitfields

• [7:0] EXT_SENS_DATA_14

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_14 @ 0x57

EXT_SENS_DATA_14 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_15 @ 0x58

Register Bitfields

• [7:0] EXT_SENS_DATA_15

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_15 @ 0x58

EXT_SENS_DATA_15 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_16 @ 0x59

Register Bitfields

• [7:0] EXT_SENS_DATA_16

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_16 @ 0x59

EXT_SENS_DATA_16 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_17 @ 0x5A

Register Bitfields

• [7:0] EXT_SENS_DATA_17

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_17 @ 0x5A

EXT_SENS_DATA_17 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_18 @ 0x5B

Register Bitfields

• [7:0] EXT_SENS_DATA_18

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_18 @ 0x5B

EXT_SENS_DATA_18 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_19 @ 0x5C

Register Bitfields

• [7:0] EXT_SENS_DATA_19

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_19 @ 0x5C

EXT_SENS_DATA_19 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_20 @ 0x5D

Register Bitfields

• [7:0] EXT_SENS_DATA_20

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_20 @ 0x5D

EXT_SENS_DATA_20 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_21 @ 0x5E

Register Bitfields

• [7:0] EXT_SENS_DATA_21

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_21 @ 0x5E

EXT_SENS_DATA_21 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_22 @ 0x5F

Register Bitfields

• [7:0] EXT_SENS_DATA_22

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_22 @ 0x5F

EXT_SENS_DATA_22 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_23 @ 0x60

Register Bitfields

• [7:0] EXT_SENS_DATA_23

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

EXT_SENS_DATA_23 @ 0x60

EXT_SENS_DATA_23 [7:0]

These registers store data read from external sensors by the Slave 0, 1, 2, and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in I2C_SLV4_DI (Register 53). For more information, see EXT_SENS_DATA_00.

Motion Detection Status (MOT_DETECT_STATUS @ 0x61)

Register Bitfields

• [7] MOT_XNEG
• [6] MOT_XPOS
• [5] MOT_YNEG
• [4] MOT_YPOS
• [3] MOT_ZNEG
• [2] MOT_ZPOS
• [0] MOT_ZRMOT

This register reports the status of Motion detection and Zero Motion detection. The Motion detection bits, MOT_XNEG, MOT_XPOS, MOT_YNEG, MOT_YPOS, MOT_ZNEG, and MOT_ZPOS, report the axis and polarity of motion which generated a Motion Detection interrupt.The MOT_ZRMOT bit is set to 1 when Zero Motion has been detected. Reading this register clears the Motion detection bits. However, the MOT_ZRMOT bit does not clear until Zero Motion is no longer detected.For more information regarding Motion detection and Zero Motion detection, please refer to Registers 31 to 34 in this document, as well as Sections 8.3 and 8.4 of the MPU-6000/MPU-6050 Product Specification document.

MOT_DETECT_STATUS @ 0x61

MOT_XNEG [7]

This bit automatically sets to 1 when motion in the negative X axis has generated a Motion detection interrupt.

MOT_DETECT_STATUS @ 0x61

MOT_XPOS [6]

This bit automatically sets to 1 when motion in the positive X axis has generated a Motion detection interrupt.

MOT_DETECT_STATUS @ 0x61

MOT_YNEG [5]

This bit automatically sets to 1 when motion in the negative Y axis has generated a Motion detection interrupt.

MOT_DETECT_STATUS @ 0x61

MOT_YPOS [4]

This bit automatically sets to 1 when motion in the positive Y axis has generated a Motion detection interrupt.

MOT_DETECT_STATUS @ 0x61

MOT_ZNEG [3]

This bit automatically sets to 1 when motion in the negative Z axis has generated a Motion detection interrupt.

MOT_DETECT_STATUS @ 0x61

MOT_ZPOS [2]

This bit automatically sets to 1 when motion in the positive Z axis has generated a Motion detection interrupt.

MOT_DETECT_STATUS @ 0x61

MOT_ZRMOT [0]

This bit automatically sets to 1 when Zero Motion detection interrupt is generated.

I2C Slave 0 Data Out (I2C_SLV0_DO @ 0x63)

Register Bitfields

• [7:0] I2C_SLV0_DO

This register holds the output data written into Slave 0 when Slave 0 is set to write mode. For further information regarding Slave 0 control, please refer to Registers 37 to 39.

I2C_SLV0_DO @ 0x63

I2C_SLV0_DO [7:0]

8 bit unsigned value that is written into Slave 0 when Slave 0 is set to write mode.

I2C Slave 1 Data Out (I2C_SLV1_DO @ 0x64)

Register Bitfields

• [7:0] I2C_SLV1_DO

This register holds the output data written into Slave 1 when Slave 1 is set to write mode. For further information regarding Slave 1 control, please refer to Registers 40 to 42.

I2C_SLV1_DO @ 0x64

I2C_SLV1_DO [7:0]

8 bit unsigned value that is written into Slave 1 when Slave 1 is set to write mode.

I2C Slave 2 Data Out (I2C_SLV2_DO @ 0x65)

Register Bitfields

• [7:0] I2C_SLV2_DO

This register holds the output data written into Slave 2 when Slave 2 is set to write mode. For further information regarding Slave 2 control, please refer to Registers 43 to 45.

I2C_SLV2_DO @ 0x65

I2C_SLV2_DO [7:0]

8 bit unsigned value that is written into Slave 2 when Slave 2 is set to write mode.

I2C Slave 3 Data Out (I2C_SLV3_DO @ 0x66)

Register Bitfields

• [7:0] I2C_SLV3_DO

This register holds the output data written into Slave 3 when Slave 3 is set to write mode. For further information regarding Slave 3 control, please refer to Registers 46 to 48.

I2C_SLV3_DO @ 0x66

I2C_SLV3_DO [7:0]

8 bit unsigned value that is written into Slave 3 when Slave 3 is set to write mode.

I2C Master Delay Control (I2C_MST_DELAY_CTRL @ 0x67)

Register Bitfields

• [7] DELAY_ES_SHADOW
• [4] I2C_SLV4_DLY_EN
• [3] I2C_SLV3_DLY_EN
• [2] I2C_SLV2_DLY_EN
• [1] I2C_SLV1_DLY_EN
• [0] I2C_SLV0_DLY_EN

This register is used to specify the timing of external sensor data shadowing. The register is also used to decrease the access rate of slave devices relative to the Sample Rate.When DELAY_ES_SHADOW is set to 1, shadowing of external sensor data is delayed until all data has been received. When I2C_SLV4_DLY_EN, I2C_SLV3_DLY_EN, I2C_SLV2_DLY_EN, I2C_SLV1_DLY_EN, and I2C_SLV0_DLY_EN are enabled, the rate of access for the corresponding slave devices is reduced.When a slave’s access rate is decreased relative to the Sample Rate, the slave is accessed every:1 / (1 + I2C_MST_DLY)samples. This base Sample Rate in turn is determined by SMPLRT_DIV (register 25) and DLPF_CFG (register 26).For further information regarding I2C_MST_DLY, please refer to register 52. For further information regarding the Sample Rate, please refer to register 25. Bits 6 and 5 are reserved.

I2C_MST_DELAY_CTRL @ 0x67

DELAY_ES_SHADOW [7]

When set, delays shadowing of external sensor data until all data has been received.

I2C_MST_DELAY_CTRL @ 0x67

I2C_SLV4_DLY_EN [4]

When enabled, slave 4 will only be accessed at a decreased rate.

I2C_MST_DELAY_CTRL @ 0x67

I2C_SLV3_DLY_EN [3]

When enabled, slave 3 will only be accessed at a decreased rate.

I2C_MST_DELAY_CTRL @ 0x67

I2C_SLV2_DLY_EN [2]

When enabled, slave 2 will only be accessed at a decreased rate.

I2C_MST_DELAY_CTRL @ 0x67

I2C_SLV1_DLY_EN [1]

When enabled, slave 1 will only be accessed at a decreased rate.

I2C_MST_DELAY_CTRL @ 0x67

I2C_SLV0_DLY_EN [0]

When enabled, slave 0 will only be accessed at a decreased rate.

Signal Path Reset (SIGNAL_PATH_RESET @ 0x68)

Register Bitfields

• [2] GYRO_RESET
• [1] ACCEL_RESET
• [0] TEMP_RESET

This register is used to reset the analog and digital signal paths of the gyroscope, accelerometer, and temperature sensors. The reset will revert the signal path analog to digital converters and filters to their power up configurations.Note: This register does not clear the sensor registers.Bits 7 to 3 are reserved.

SIGNAL_PATH_RESET @ 0x68

GYRO_RESET [2]

When set to 1, this bit resets the gyroscope analog and digital signal paths.

SIGNAL_PATH_RESET @ 0x68

ACCEL_RESET [1]

When set to 1, this bit resets the accelerometer analog and digital signal paths.

SIGNAL_PATH_RESET @ 0x68

TEMP_RESET [0]

When set to 1, this bit resets the temperature sensor analog and digital signal paths.

Motion Detection Control (MOT_DETECT_CTRL @ 0x69)

Register Bitfields

• [5:4] ACCEL_ON_DELAY
• [3:2] FF_COUNT
• [1:0] MOT_COUNT

This register is used to add delay to the accelerometer power on time. It is also used to configure the Free Fall and Motion detection decrement rate.The accelerometer data path provides samples to the sensor registers, Motion detection, Zero Motion detection, and Free Fall detection modules. The signal path contains filters which must be flushed on wake-up with new samples before the detection modules begin operations. The default wake-up delay, of 4ms can be lengthened by up to 3ms. This additional delay is specified in ACCEL_ON_DELAY in units of 1 LSB = 1 ms. The user may select any value above zero unless instructed otherwise by InvenSense. Please refer to Section 8 of the MPU-6000/MPU-6050 Product Specification document for further information regarding the detection modules.Detection is registered by the Free Fall detection module or the Motion detection module after accelerometer measurements meet their respective threshold conditions over a specified number of samples. When the threshold conditions are met, the corresponding detection counter increments by 1. The user may control the rate at which the detection counter decrements when the threshold condition is not met by configuring FF_COUNT and MOT_COUNT. The decrement rate can be set according to the following table:FF_COUNT or MOT_COUNT Counter Decrement0 Reset1 12 23 4When FF_COUNT or MOT_COUNT are configured to 0 (reset), any non-qualifying sample will reset the corresponding counter to 0. For further information on Free Fall detection and Motion detection, please refer to Registers 29 to 32.Bits 7 and 6 are reserved.

MOT_DETECT_CTRL @ 0x69

ACCEL_ON_DELAY [5:4]

2-bit unsigned value. Specifies the additional power-on delay applied to accelerometer data path modules. Unit of 1 LSB = 1 ms.

MOT_DETECT_CTRL @ 0x69

FF_COUNT [3:2]

Options

• 0 = Reset
• 1 = 1
• 2 = 2
• 3 = 4

2-bit unsigned value. Configures the Free Fall detection counter decrement rate.

MOT_DETECT_CTRL @ 0x69

MOT_COUNT [1:0]

Options

• 0 = Reset
• 1 = 1
• 2 = 2
• 3 = 4

2-bit unsigned value. Configures the Motion detection counter decrement rate.

User Control (USER_CTRL @ 0x6A)

Register Bitfields

• [7] DMP_EN
• [6] FIFO_EN
• [5] I2C_MST_EN
• [4] I2C_IF_DIS
• [3] DMP_RESET
• [2] FIFO_RESET
• [1] I2C_MST_RESET
• [0] SIG_COND_RESET

This register allows the user to enable and disable the FIFO buffer, I2C Master Mode, and primary I2C interface. The FIFO buffer, I2C Master, sensor signal paths and sensor registers can also be reset using this register.When I2C_MST_EN is set to 1, I2C Master Mode is enabled. In this mode, the MPU-60X0 acts as the I2C Master to the external sensor slave devices on the auxiliary I2C bus. When this bit is cleared to 0, the auxiliary I2C bus lines (AUX_DA and AUX_CL) are logically driven by the primary I2C bus (SDA and SCL). This is a precondition to enabling Bypass Mode. For further information regarding Bypass Mode, please refer to Register 55.MPU-6000: The primary SPI interface will be enabled in place of the disabled primary I2C interface when I2C_IF_DIS is set to 1.MPU-6050: Always write 0 to I2C_IF_DIS.When the reset bits (DMP_RESET, FIFO_RESET, I2C_MST_RESET, and SIG_COND_RESET) are set to 1, these reset bits will trigger a reset and then clear to 0.

USER_CTRL @ 0x6A

DMP_EN [7]

When set to 1, this bit enables Digital Motion Processor (DMP) operations.

USER_CTRL @ 0x6A

FIFO_EN [6]

When set to 1, this bit enables FIFO operations. When this bit is cleared to 0, the FIFO buffer is disabled. The FIFO buffer cannot be written to or read from while disabled. The FIFO buffer’s state does not change unless the MPU-60X0 is power cycled.

USER_CTRL @ 0x6A

I2C_MST_EN [5]

When set to 1, this bit enables I2C Master Mode. When this bit is cleared to 0, the auxiliary I2C bus lines (AUX_DA and AUX_CL) are logically driven by the primary I2C bus (SDA and SCL).

USER_CTRL @ 0x6A

I2C_IF_DIS [4]

MPU-6000: When set to 1, this bit disables the primary I2C interface and enables the SPI interface instead.MPU-6050: Always write this bit as zero.

USER_CTRL @ 0x6A

DMP_RESET [3]

This bit resets the DMP engine when set to 1 while DMP_EN equals 0. This bit automatically clears to 0 after the reset has been triggered.

USER_CTRL @ 0x6A

FIFO_RESET [2]

This bit resets the FIFO buffer when set to 1 while FIFO_EN equals 0. This bit automatically clears to 0 after the reset has been triggered.

USER_CTRL @ 0x6A

I2C_MST_RESET [1]

This bit resets the I2C Master when set to 1 while I2C_MST_EN equals 0. This bit automatically clears to 0 after the reset has been triggered.

USER_CTRL @ 0x6A

SIG_COND_RESET [0]

When set to 1, this bit resets the signal paths for all sensors (gyroscopes, accelerometers, and temperature sensor). This operation will also clear the sensor registers. This bit automatically clears to 0 after the reset has been triggered.When resetting only the signal path (and not the sensor registers), please use Register 104, SIGNAL_PATH_RESET.

Power Management 1 (PWR_MGMT_1 @ 0x6B)

Register Bitfields

• [7] DEVICE_RESET
• [6] SLEEP
• [5] CYCLE
• [3] TEMP_DIS
• [2:0] CLK_SEL

This register allows the user to configure the power mode and clock source. It also provides a bit for resetting the entire device, and a bit for disabling the temperature sensor.By setting SLEEP to 1, the MPU-60X0 can be put into low power sleep mode. When CYCLE is set to 1 while SLEEP is disabled, the MPU-60X0 will be put into Cycle Mode. In Cycle Mode, the device cycles between sleep mode and waking up to take a single sample of data from active sensors at a rate determined by LP_WAKE_CTRL (register 108). To configure the wake frequency, use LP_WAKE_CTRL within the Power Management 2 register (Register 108).An internal 8MHz oscillator, gyroscope based clock, or external sources can be selected as the MPU-60X0 clock source. When the internal 8 MHz oscillator or an external source is chosen as the clock source, the MPU-60X0 can operate in low power modes with the gyroscopes disabled.Upon power up, the MPU-60X0 clock source defaults to the internal oscillator. However, it is highly recommended that the device be configured to use one of the gyroscopes (or an external clock source) as the clock reference for improved stability. The clock source can be selected according to the following table:CLKSEL Clock Source0 Internal 8MHz oscillator1 PLL with X axis gyroscope reference2 PLL with Y axis gyroscope reference3 PLL with Z axis gyroscope reference4 PLL with external 32.768kHz reference5 PLL with external 19.2MHz reference6 Reserved7 Stops the clock and keeps the timing generator in resetFor further information regarding the MPU-60X0 clock source, please refer to the MPU-6000/MPU-6050 Product Specification document.Bit 4 is reserved.

PWR_MGMT_1 @ 0x6B

DEVICE_RESET [7]

When set to 1, this bit resets all internal registers to their default values. The bit automatically clears to 0 once the reset is done.The default values for each register can be found in Section 3.

PWR_MGMT_1 @ 0x6B

SLEEP [6]

When set to 1, this bit puts the MPU-60X0 into sleep mode. Note: default power-on state for MPU-60X0 is in sleep mode.

PWR_MGMT_1 @ 0x6B

CYCLE [5]

When this bit is set to 1 and SLEEP is disabled, the MPU-60X0 will cycle between sleep mode and waking up to take a single sample of data from active sensors at a rate determined by LP_WAKE_CTRL (register 108).

PWR_MGMT_1 @ 0x6B

TEMP_DIS [3]

When set to 1, this bit disables the temperature sensor.

PWR_MGMT_1 @ 0x6B

CLK_SEL [2:0]

Options

• 0 = Internal 8MHz oscillator
• 1 = PLL with X axis gyroscope reference
• 2 = PLL with Y axis gyroscope reference
• 3 = PLL with Z axis gyroscope reference
• 4 = PLL with external 32.768kHz reference
• 5 = PLL with external 19.2MHz reference
• 6 = RESERVED
• 7 = Clock stopped, timing generator in reset

3-bit unsigned value. Specifies the clock source of the device.The clock source can be selected according to the following table:CLKSEL Clock Source0 Internal 8MHz oscillator1 PLL with X axis gyroscope reference2 PLL with Y axis gyroscope reference3 PLL with Z axis gyroscope reference4 PLL with external 32.768kHz reference5 PLL with external 19.2MHz reference6 Reserved7 Stops the clock and keeps the timing generator in reset

Power Management 2 (PWR_MGMT_2 @ 0x6C)

Register Bitfields

• [7] LP_WAKE_CTRL
• [5] STBY_ZG
• [4] STBY_YA
• [3] STBY_ZA
• [2] STBY_XG
• [1] STBY_YG
• [0] STBY_ZG

This register allows the user to configure the frequency of wake-ups in Accelerometer Only Low Power Mode. This register also allows the user to put individual axes of the accelerometer and gyroscope into standby mode.The MPU-60X0 can be put into Accerlerometer Only Low Power Mode by setting PWRSEL to 1 in the Power Management 1 register (Register 107). In this mode, the device will power off all devices except for the primary I2C interface, waking only the accelerometer at fixed intervals to take a single measurement. The frequency of wake-ups can be configured with LP_WAKE_CTRL as shown below:LP_WAKE_CTRL Wake-up Frequency0 1.25 Hz1 2.5 Hz2 5 Hz3 10 HzFor further information regarding the MPU-9150’s power modes, please refer to Register 107.The user can put individual accelerometer and gyroscopes axes into standby mode by using this register. If the device is using a gyroscope axis as the clock source and this axis is put into standby mode, the clock source will automatically be changed to the internal 8MHz oscillator.

PWR_MGMT_2 @ 0x6C

LP_WAKE_CTRL [7]

Options

• 0 = 1.25 Hz
• 1 = 2.5 Hz
• 2 = 5 Hz
• 3 = 10 Hz

2-bit unsigned value. Specifies the frequency of wake-ups during Accelerometer Only Low Power Mode.

PWR_MGMT_2 @ 0x6C

STBY_ZG [5]

When set to 1, this bit puts the X axis accelerometer into standby mode.

PWR_MGMT_2 @ 0x6C

STBY_YA [4]

When set to 1, this bit puts the Y axis accelerometer into standby mode.

PWR_MGMT_2 @ 0x6C

STBY_ZA [3]

When set to 1, this bit puts the Z axis accelerometer into standby mode.

PWR_MGMT_2 @ 0x6C

STBY_XG [2]

When set to 1, this bit puts the X axis gyroscope into standby mode.

PWR_MGMT_2 @ 0x6C

STBY_YG [1]

When set to 1, this bit puts the Y axis gyroscope into standby mode.

PWR_MGMT_2 @ 0x6C

STBY_ZG [0]

When set to 1, this bit puts the Z axis gyroscope into standby mode.

Memory Bank Selection (BANK_SEL @ 0x6D)

Register Bitfields

• [6] PRFTCH_EN
• [5] CFG_USER_BANK
• [4:0] MEM_SEL

Memory Start Address (MEM_START_ADDR @ 0x6E)

Register Bitfields

• [7:0] START_ADDR

Memory Read/Write (MEM_R_W @ 0x6F)

Register Bitfields

• [7:0] MEM_R_W

MEM_R_W @ 0x6F

Memory Read/Write (MEM_R_W [7:0])

DMP Configuration 1 (DMP_CFG_1 @ 0x70)

DMP Configuration 2 (DMP_CFG_2 @ 0x71)

FIFO Count High Byte (FIFO_COUNTH @ 0x72)

Register Bitfields

• [15:0] FIFO_COUNT

These registers keep track of the number of samples currently in the FIFO buffer. These registers shadow the FIFO Count value. Both registers are loaded with the current sample count when FIFO_COUNT_H (Register 72) is read.Note: Reading only FIFO_COUNT_L will not update the registers to the current sample count. FIFO_COUNT_H must be accessed first to update the contents of both these registers.FIFO_COUNT should always be read in high-low order in order to guarantee that the most current FIFO Count value is read.

FIFO_COUNTH @ 0x72

FIFO_COUNT [15:0]

16-bit unsigned value. Indicates the number of bytes stored in the FIFO buffer. This number is in turn the number of bytes that can be read from the FIFO buffer and it is directly proportional to the number of samples available given the set of sensor data bound to be stored in the FIFO (register 35 and 36).

FIFO Count Low Byte (FIFO_COUNTL @ 0x73)

FIFO Read/Write (FIFO_R_W @ 0x74)

Register Bitfields

• [7:0] FIFO_R_W

This register is used to read and write data from the FIFO buffer. Data is written to the FIFO in order of register number (from lowest to highest). If all the FIFO enable flags (see below) are enabled and all External Sensor Data registers (Registers 73 to 96) are associated with a Slave device, the contents of registers 59 through 96 will be written in order at the Sample Rate.The contents of the sensor data registers (Registers 59 to 96) are written into the FIFO buffer when their corresponding FIFO enable flags are set to 1 in FIFO_EN (Register 35). An additional flag for the sensor data registers associated with I2C Slave 3 can be found in I2C_MST_CTRL (Register 36).If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is automatically set to 1. This bit is located in INT_STATUS (Register 58). When the FIFO buffer has overflowed, the oldest data will be lost and new data will be written to the FIFO.If the FIFO buffer is empty, reading this register will return the last byte that was previously read from the FIFO until new data is available. The user should check FIFO_COUNT to ensure that the FIFO buffer is not read when empty.

FIFO_R_W @ 0x74

FIFO_R_W [7:0]

8-bit data transferred to and from the FIFO buffer.

WHO_AM_I @ 0x75

Register Bitfields

• [6:1] WHO_AM_I

This register is used to verify the identity of the device. The contents of WHO_AM_I are the upper 6 bits of the MPU-60X0’s 7-bit I2C address. The least significant bit of the MPU-60X0’s I2C address is determined by the value of the AD0 pin. The value of the AD0 pin is not reflected in this register.The default value of the register is 0x68.Bits 0 and 7 are reserved. (Hard coded to 0)

WHO_AM_I @ 0x75

WHO_AM_I [6:1]

Contains the 6-bit I2C address of the MPU-60X0. The Power-On-Reset value of Bit6:Bit1 is 110 100.